Loopback testing is often used to confirm operability of transmit and/or receive circuits within signal transceivers. In a typical loopback testing arrangement, a pseudorandom bit sequence (PRBS) generator delivers a sequence of test data values to the transmit circuit. The transmit circuit outputs a corresponding test data signal onto a signal path. The signal path is looped-back to the input of a receiver circuit. The receiver circuit may include a sampling flip-flop, that is driven by a sampling clock, to sample the test data signal. In particular, the sampling flip-flop samples the incoming test data signal (according to the timing of the sampling clock) to generate a sequence of received data values. The test data sequence of the test data signal and the received data sequence can then be compared bit-for-bit to confirm whether or not there is error-free signal transmission and reception. If bit errors are not detected, this means that the received data sequence corresponds to the original test data sequence of the test data signal, and that the result of the loopback test is no error. If bit errors) are detected, an error can be signaled to indicate a mismatch between the test data sequence of the test data signal and the received data sequence.
For a loopback testing to work correctly, the sampling clock that drives the sampling flip-flop should ideally be phase aligned with respect to the test data signal that is being used to perform loopback testing. However, this can become problematic when the loopback data path is relatively long and/or different output driver modes need to be supported. Either factor can result in large round-trip delay variation. This is especially true in high data rate systems (e.g., those with a data rate of 5.4 Gigabytes per second or greater) since the timing margin left to meet setup and hold time requirements of sampling flip-flop is limited.
In addition, variations in the fabrication process used to manufacture the transmitter can also make it difficult to phase align the sampling clock (that drives the sampling flip-flop) with respect to the test data signal.
In some complex devices, such as transceivers that have a high-speed bi-directional interface between a transmitter and a receiver for loopback testing, a clock recovery circuit or digital-to-analog converter (DAC)-controlled phase interpolator can be provided at the receiver. For example, in some implementations, a clock recovery circuit used at a receiver can include a digital-to-analog converter (DAC)-controlled phase interpolator to accurately align the sampling phase of the sampling clock with respect to the phase of the test data signal.
Another option for loopback testing is to employ an external high-speed test receiver. Some external high-speed test receivers include a clock recovery circuit or adjustable chain of delay elements in series with sampling clock that can be used to align the phase of the sampling clock with respect to the phase of the test data signal. The external high-speed test receiver can be less desirable since it is a separate piece of equipment that is not integrated as part of the device, and adds additional cost and complexity when implementing loopback testing.
With other types of devices, such as uni-directional physical layer devices that have a transmitter only, a test receiver can be implemented to perform loopback testing with respect to the transmitter. However, it may be undesirable to incorporate a dedicated clock recovery circuit at the test receiver for the sole purpose of testing the functionality of the transmit path. For example, it may be cost prohibitive or impractical due to the relatively limited die area and increased design complexity. This is particularly true when the test receiver is implemented as an internal, on-die component that is integrated with the device since the available die area that can be used to implement the test receiver is limited, which makes inclusion of a clock recovery circuit undesirable in many devices.